1. Field of the Invention
The present invention relates to a CCD (Charge Coupled Devices) type solid state imaging device and an output circuit thereof, and more particularly to a solid state imaging device which can suppress a deterioration in S/N and an output circuit thereof.
2. Description of the Related Art
In a CCD type solid state imaging device, each signal charge detected by each pixel (photoelectric converting device) is transferred to a charge detecting portion (floating diffusion (FD) portion) of an end of a horizontal charge transfer path through the transfer path and the charge detecting portion converts an amount of the signal charge into a voltage value. An output circuit current amplifies a voltage value signal by a three-stage source follower and outputs the signal as a pickup image signal as described in JP-A-2002-335449 and JP-A-2006-165290, for example. A related CCD type solid state imaging device described in JP-A-2006-165290 is illustrated in FIG. 5. The CCD type solid state imaging device illustrated in FIG. 5 includes vertical CCDs 44, horizontal CCDs 46, reading gates 42, and photosensitive units 40 on a semiconductor substrate 50.
FIG. 3 is a circuit diagram showing an example of the related-art output circuit. A signal charge transferred from each pixel which is not shown enters a charge detecting portion (FD portion) 11 provided on an end of a horizontal charge transfer path which is not shown and is converted into a voltage. The voltage is current amplified by a three-stage source follower circuit 12 and is output as a pickup image signal from an output terminal OS.
The signal charge stored in the FD portion 11 and converted into the voltage is discharged to a reset drain (RD) via a reset transistor 13 set in a conducting state by an application of a reset pulse to a gate (RG) of a reset transistor 13.
A proper bias voltage is usually applied to the gate (RG) of the reset transistor 13 through an external circuit. In an example shown in the drawing, the bias voltage is applied by a bias voltage generating circuit 14 provided in an imaging device in order to cause the external circuit to be unnecessary.
The bias voltage generating circuit 14 is constituted by an enhancement type MOS transistor 15 and a depression type MOS transistor 16 which are connected in series between a power supply OD (voltage Vdd) and a ground.
A resistor (for example, 30 kΩ) having a proper magnitude is provided in the imaging device in such a manner that a pulse voltage is properly applied to the reset transistor 13 between a node of both of the transistors 15 and 16 of the bias voltage generating circuit 14 and the reset gate (RG).
Moreover, a coupling capacitor (for example, 0.1 μF) having a proper magnitude is provided between the reset gate (RG) and a reset pulse generating circuit 18 to be an external circuit in such a manner that a pulse voltage is properly applied to the reset transistor 13.
In the output circuit, when the reset pulse generating circuit 18 generates a pulse having a low voltage of [0V/3.3V] and the same pulse is applied to the reset gate RG, the bias voltage is applied to the reset gate RG through a resistor 17. When the source voltage (OD) reaches 15V, therefore, a pulse having a high voltage of [12V/15V] is applied to the reset gate RG.
FIG. 4 is a graph showing a result obtained by carrying out a circuit simulation when a power supply is turned ON in the output circuit of FIG. 3 by using a typical parameter. The case in which a voltage of a power supply (OD, RD) rises from 5V to 15V at 30 μs is calculated.
It is apparent that a rise in a voltage Vrg of the reset gate RG is much gentler than a rise in the supply voltage Vdd. The reason is that a coupling capacitor 19 connected to the reset gate RG is charged through the resistor 17. A time of approximately 2.2 RC (2.2 ms:0.2 ms which is one-tenth of 2.2 ms is shown at a maximum in an axis of abscissas in the graph) is taken before an electric potential of the reset gate RG rises completely.
As a gate voltage Vg1 of an initial stage drive transistor 21 of the three-stage source follower circuit 12, a voltage obtained by adding vth of the reset transistor 13 to a reset gate voltage Vrg is applied. As a result, the time is taken for a rising time of a source voltage Vs1 of the initial stage drive transistor 21.
In the case in which a rise in the electric potential Vrg of the reset gate RG is gentler than a rise in the electric potential of the power supply OD, accordingly, a difference (VDS1) between the power supply OD and a source voltage Vs1 of the initial stage drive transistor 21 is increased immediately after the power supply is turned ON.
In the case in which an electric potential difference VDS1 between a drain and a source is great, thus, a deterioration in a performance of the transistor is caused by the generation of a hot electron. For example, the hot electron collides with a gate film so that an interface state density is generated on an interface of a silicon/gate film and serves as a noise source, resulting in a deterioration in S/N of an image quality of a pickup image.
In order to avoid the deterioration, it is preferable to simply decrease a resistance value of the bias voltage generating circuit 14 or a capacity of the capacitor. However, there is a problem in that an amplitude of a reset pulse is reduced as a side effect. For this reason, it is necessary to quicken the rise in the voltage Vrg of the reset gate without varying the resistance and the capacity.